(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )

CN · Suzhou · Suzhou, Jiangsu, China · On-site in China · Full-time · Senior

中国时区，需配合团队工作

On-site in ChinaSeniorOpen to China

Salary not stated

package designpower SiP/modulewafer level packagingflip-chip packagingSPCstatistical analysisDOEprocess qualificationwire-bondingmulti-chip module

Excerpt

Company Description Job Summary • Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, wafer level, flip-chip, multi-chip module and power device packaging, GaN related PKG is a plus. • Package technologies qualification for consumer &…

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