(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )

CN · Shanghai · Shanghai, Shanghai, China · On-site in China · Full-time · Senior

On-site in ChinaSeniorOpen to China

Salary not stated

package designpower SiP/moduleswafer level packagingflip-chip packagingprocess optimizationDOESPCstatistical analysismaterial qualificationreliability testingmulti-chip modulewire-bondingpanel level package

Excerpt

Company Description Job Summary • Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, wafer level, flip-chip, multi-chip module and power device packaging, GaN related PKG is a plus. • Package technologies qualification for consumer &…

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